Atomistic Multiscale Simulation-Based Extraction of Design Margins in Advanced Transistor Architectures

Employing Kinetic Monte Carlo (KMC) method for epitaxy simulation reinforced with Molecular Dynamics for KMC model parameter extraction, this study establishes an approach for determining design margins in transistor architectures characterized by high aspect ratio cavities. This integrated atomistic and multiscale simulation framework allows prediction of the epitaxy quality and potential defects as well as the optimization of key design parameters.