Wafer Edge and Backside Profile Integration with 3-D Process Emulation

Attention has been drawn on wafer front surface's patterning area while developing next-generation semiconductor products. Unfortunately, to enhance device performance, the number of process steps and integration schemes are diversified inducing complex patterns over whole surfaces including wafer edge and back-side (WEB) in final. Thus, focusing on those regions is required beyond the front, as defects and process risks are increased on the regions. So far, post-processes are executed to reduce defects after their occurrence at the edges and back-side, but it is important to understand defect generation mechanism to suppress them effectively. In this paper, we utilized 3-D process emulation on WEB profile integration to estimate defect risk in early stage of product development before defect occurs. In final, WEB profile has been integrated and consistent with real-wafer's cross-section microscopy images with typical defect sources.