Barrier-Less W Metallization Processes for Low-Resistance Contacts at Sub-3 nm Logic Devices

The low-resistance of middle of line (MOL) contacts has been highlighted as critical for high-performance logic devices. Tungsten (W) has been widely used in MOL, but the relevantly required barrier materials (e.g. TiN) prevented achieving low resistance contacts as the dimension shrinks down. The replacement of high resistance barrier by an enhanced PVD W technology with an excellent step coverage allowed barrier-less W process, but a limited gap-fill performance of PVD W alone is still challenging for ultra-high aspect ratio contacts at sub-3 nm logic devices. In this study, a novel fabrication route of low-resistance barrier-less W contacts has been freshly demonstrated by reinforcing the combination of PVD W and CVD W with an adoption of nucleation process. The result of ASTAR TEM analysis exhibits a single crystallographic orientation in each contact, which is desirable for the low resistivity and reliability. Furthermore, the nucleation-assisted barrier-less W shows dramatically reduced contact resistance compared to the conventional W metallization with barrier, which resulted in significant gain of AC performance in logic devices. The suggested barrier-less W metallization process is strongly believed to be more efficiently applicable to high-performance sub-3 nm logic devices.