Implementation of Efficient Low Power SHA-256 Algorithm

Secure Hash Algorithm-256 (SHA-256) is widely used in many applications for its high level of security. Many authors have worked on increasing the frequency and throughput of SHA -256 using carry save adder, variable pre-computation and loop unrolling. But applications like RFID and IoT require low power design of SHA-256 where there is constraint on the power. Also, most of the authors have focused on the usage of one type of adder that is Carry Save Adder(CSA). In proposed design, Carry Look Ahead adder(CLA) and Carry Skip Adder(CSkA) are used in the SHA-256 hardware design. Experiment results show that SHA-256 using CLA and CSkA in the critical computational path reduces power, area and delay compared to the CSA. However, in case of CSA, the power is further reduced by using clock gating and power gating techniques to 4.05074mW. Considering the previous works on SHA-256 algorithm, this is the least power achieved in ASIC.