Exploring energy efficient area optimized one-bit full Subtractor circuit for Signal processing application using CMOS and FinFET Technology

Today's VLSI design places a great deal of importance on static or leaky power usage as technology advances into the nanoscale realm. Energy efficiency is a significant key factor for several integrated circuits. In the world of modern integrated circuits (ICs) that operate in near-threshold voltage (NTV) is gaining much attention because of its potential for high-performance and energy-efficient designs. In this brief, a 1-bit full subtractor (FS) cell with reduced transistor count is suggested for lower power application by employing C-CMOS and FINFET schemes at different supply voltages for achieving full swing difference and borrows output. A number of metrics, including delay, power consumption, PDP and EDP have been ascertained from the 45nm and 18nm feature size technology node for the implemented circuits both in CMOS and FinFET. The outcomes demonstrate how efficient the FS cell can serve as an arithmetic circuit for unconventional signal processing computing applications in integrated circuits (ICs).