Design and Implementation of Pipelined MIPS Processor with Nested Vectored Interrupt Controller (NVIC)

MIPS (abbr. Microprocessor without Interlocked Pipelined Stages) based Pipelined Processor is a RISC (Reduced Instruction Set Computer) Processor [1][2]. The Processor is a 32-bit RISC Processor with the Data and Address Bus of 32-bit width. The Processor uses five hardware stages for its operation - Instruction Fetch (IF), Decode (ID), Execution (EX), Memory Access (MEM), and Write Back (WB). Pipelining is used to increase the instruction throughput thereby achieving efficient Performance. The Instruction Set Architecture for the MIPS is divided into 3 categories of Instruction Format - Register Type (R-type), Immediate Type (I-type), and Jump/Branch Type (J-type) [4][5]. Each of these Instruction types is characterized by distinct opcodes, source/destination register fields, shift amount, function, etc. Although there are inherent advantages of Pipelining, it also introduces Hazards due to the dependencies that occur between stages such as - Data Hazards, Control Hazards, Structural Hazards, etc. A dedicated forwarding unit solves this problem. The RTL is written in the Verilog Hardware Description Language (HDL) for several different modules such as the Memory, Register File, ALU as well as other key modules such as Forwarding Unit, Hazard Detection Unit, Stall Control Unit, etc. for solving Hazards and numerous other modules for the realization of the Pipelined MIPS Processor. The simulation is carried out using a set number of Instructions to realize the proper operation of the Processor with Pipelined execution. The second part of this Project activity is the design of a Nested Vectored Interrupt Controller (NVIC) [3][7]. The NVIC is used to provide the Nested Interrupt support. The NVIC can be operated in the Default mode as well as the Priority mode. The Priority mode can be used to program all the Internal/External Interrupts to different Priority levels. The RTL is written for both the MIPS Processor and the NVIC in the Intel Quartus® Prime FPGA Design Software. The Simulation is carried out using ModelSim HDL Simulator. This Design supports building robust applications making use of the Processor. The realization of complex applications is destined to be the part of Future Scope for this particular Processor design.