An Effective Method to Develop Pseudo Ntype-GNRFETs based Digital Circuits in Ternary Logic

Ternary logic systems are predominantly intriguing for nano-scaling design because of various advantages, including increased density and faster operation which may be accomplished with emerging technologies. In this work, a novel unbalanced ternary circuit designs that makes use of graphene nanoribbon transistors (GNRFETs) are presented. The Pseudo N-GNRFET technique is used in the proposed inverters, universal gates and half adder, respectively. This approach ensures that ternary logic circuits perform properly by regulating the threshold voltages of P - and N - transistors. The threshold voltages of these transistors are determined by the GNR dimer line number. When compared to complimentary schematics the proposed ternary designs reduced power consumption by 39.78%, propagation delay by 47.22%, and power-delay-product (PDP) by 94.59%, respectively.