A 5.4mW 12GHz Quadrature VCO using current reusing technique in 28nm CMOS technology

The quadrature clock (IQ) generation scheme is very important in high-speed SERDES or general 4-way interleaved systems. In this work, a current reusing technique has been exploited, by stacking the VCO, divider, and output buffers. Also, an NMOS/PMOS cross-coupled pair has been used for VCO, which generates a higher 2x swing, unlike the CMOS VCO. A novel digital on/off momcapacitor switch is proposed to minimize its contribution to the VCO phase noise during the ‘off’ state. The proposal has inherent voltage regulation action resulting in a better PSRR. A prototype has been implemented in 16nm FF technology, which has a 24GHz VCO, and a 12GHz IQ clock divider. The circuit consumes 5.4mW power from a 1.0V supply. The phase noise of the 12GHz carrier frequency at 1MHz offset is -110dBc/Hz while achieving an FOM of -187.5dBc at 1MHz offset. A frequency pushing of 100kHz has been simulated for a 5mV pk-pk 10MHz supply noise.