Distributed Arithmetic Based FIR Filter: FPGA Implementation

In this paper, a Distributed Arithmetic (DA) method for reconfigurable digital filters with finite impulse response (FIR) on FPGA is presented. The inherent parallelism of the DA architecture is used to optimize resource efficiency and performance. A conventional method with a comparable filter length is contrasted with the Distributed Arithmetic-based FIR filter design. It is found that, compared to normal FIR filters, DA filters require fewer LUTs and flip-flops, and no LUT RAM for memory storage or other implementation components. A useful tool for scientists and engineers involved in digital audio processing and communications is the suggested Verilog implementation.