Design of Novel Phase Frequency Detectors for Low Phase Noise Frequency Multipliers

Phase frequency detectors (PFDs), which are utilized in Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs), are an essential component of any frequency synthesizer systems. DLL is made up of four parts: PFD, CP, VCDL, and EC, with PFD playing a crucial role in identifying phase differences between the reference and feedback signals. Having a lot of parameters controlling the PFD output, it becomes necessary to understand each of them and have a balanced design, which determines having low trade-offs. This research proposes four innovative PFDs that outperformed their parent PFDs. Analysis on power, phase noise, corner analysis, and sweep analysis (frequency) are performed to offer a clear picture of trade-offs. PFD performance is demonstrated using a gpdk90 nm CMOS technology and voltage range between $1 \mathrm{~V}-\mathbf{1. 8 V}$. The analysis findings demonstrated a 39.12% reduction in power consumption for the suggested NL-PFD, as well as a 55.5% decrease in dead zone operating frequency for the buffer-based PFD, while in terms of phase noise we see a decrease of 9.7% for NL-PFD design. Other two unique designs have also demonstrated considerable results in terms of transistor count, power consumption, and dead zone trade-offs.