A Statistically Evaluated Decision Tree Approach for SI-Compliant PCB Design

Constantly decreasing switching times in electronic systems lead to EMC problems such as signal integrity (SI)-noise and make it difficult for the PCB designer to find an adequate solution within the available parameter space. AI algorithms are very promising to find SI-compliant design parameters. Methods such as genetic algorithm (GA) or Bayesian optimization (BO) have been used to determine an optimal parameter set and support circuit design. However, the algorithms mentioned can be rather time-consuming for a large dimension of the design space, especially during the training process. Furthermore, there is generally no explanation for the results of the AI approaches available. The designer has to accept the proposed solutions without insight. In this contribution, a combined approach is presented to ensure SI-conformity. Signal waveforms describing the SI behaviour are generated for two different kind of signal networks (point-to-point and daisy chain) and are analyzed with a decision tree (DT) approach for SI-compliance. In order to obtain SI-compliant design parameters, the occurrence of the parameters is analyzed using probability mass functions. Thereby an optimum parameter set is provided as part of the available design space. The proposed method represents a simple approach due to the understandable and hierarchical structure of the decision tree (physically explainable AI).