A 18 nm FD-SOI CMOS 6.38 mW 15 fps 8 -bit features 14.8 μJ/inference QVGA road-traffic monitoring Edge AI SoC demonstrator

This paper presents an autonomous road traffic monitoring Edge AI SoC implemented in 18nm FD-SOI CMOS. The SoC includes a RISC-V CPU, a 128 Processing Elements (PE) Single Instruction Multiple Data (SIMD) Tensor Processing Unit (TPU) AI accelerator, with QVGA and control interfaces. It uses Adaptative-Body-Bias (ABB) process and temperature compensation. The circuit operates within 0.5 to $0.87 \mathrm{~V},-40$ to $140^{\circ} \mathrm{C}, 50$ to 500 MHz ranges. The TPU efficiency energy per inference and latency are $3.52 \mu \mathrm{~J}$ and 0.616 ms when running MobileNet v1 stripped by 2 layers, and $14.8 \mu \mathrm{~J}$ and 2.27 ms when running traffic monitoring application. For this latter application, the circuit total power is 6.38 mW at 15 fps 0.5 V supply.