Examining Floating Point Precision in Contemporary FPGAs

Current computer systems use an approximation of real numbers to perform calculations, which are frequently based on a particular FP (Floating-Point) format. The bit width of the relevant Fraction (F), and Exponent (E) fields determines the enhanced dynamic range and precision of FP numbers in comparison to a fixed number of points. Usually, point of floating precisions have been made available by designs like central processing units (CPUs) and Unit for Processing Graphics. These precisions were primarily bit of 16, bit of 32 and bit of 64 widths also referred to as half and single along format with double-precision. On the other hand, reconfigurable architectures, like FPGAs (Field Programmable Gate Arrays), enable creators to achieve the optimal harmony of precision, dynamic range, energy efficiency, and rapidity by enabling the implementation of nearly any required custom precision to suit certain workload types. For custom-precision floating precision, this effort suggests a recursive Chisel-based generator that can execute common yet fundamental operations including sum of two, abate of two, multiple of two, and accumulation of multiple. Specifically, it present a comprehensive preliminary investigation that illustrates the expect results on several type and generation of FPGAs, covers all elements of field of area, power, and speed.