Behavioural Modelling of Fractional-N All Digital Phase-locked Loop for Low-Power Applications

This paper discussed in detail about the behavioural model of an accumulator-based fractional-N all-digital phase-locked loop (ADPLL). A top-down and bottom-up methodology is used to model the ADPLL with the Verilog-AMS hardware description language. This methodology provides key insights and understanding into the accumulator-based ADPLL in terms of its intricate timing requirements, the effects of finite word length, and the effectiveness of the calibration process. This paper also illustrated a step-by-step modelling process using an analog-on-top approach, where all blocks are combined in a schematic in an analog environment and simulated using a commercial mixed-signal simulator.