Efficient Design and Analysis of Dual-Edge Triggered Flip-Flop for Advanced VLSI Systems

This paper has a comparative study conducted on various Flip Flop (FF) topologies flop Dual edge triggering (DET) of clock to reduce synchronous IC's dynamic power dissipation. A Static DET FF with inverters connected back to back (B2B) and a transmission gate (TG), as well as a real single phase clock static DET FF, are two different forms of latch multiplexer based DET FFs that are examined. Additionally, a C element based DET FF is examined, offering power efficiency but being more complex and error prone. To address these challenges, a proposed DET FF scheme is introduced, which is transparent when CLK=l and uses complementary static latches. It employs a Fully Static Complementary CMOS MUX for improved reliability and low voltage operations. The proposed design outperforms an earlier True Single Phase Clocked DET FF (TSPC) with 38 transistors by using 36 transistors.