Performance Comparison of High Speed and Low Power Pulse-Triggered Flip Flops and a Pulse Flip Flop with Signal Feed through Technique

This article compares the performance of four pulse-triggered flip-flops (PTFFs) implementations featuring an explicit pulse generation technique is compared in this article. It consists of explicit pulse-triggered data near the output flip-flop (ep-DCOFF), conditional discharging flip-flop (CDFF), static conditional discharging flip-flop (SCDFF), and signal feedthrough flip-flop (SFTFF). The CDFF and SCDFF both use the conditional discharge approach. This flip-flop's benefits include reduced internal switching activity, fewer output glitches, negative setup time, and less input-to-output delay feature. A signal feed-through mechanism is made possible by the true single-phase clock latch-based topology of the SFTFF. With its explicit form of pulse creation, the SFTFF mitigates the most extended discharge path issue that arises in other conservative flip-flops. Power and speed performance are improved with this design. Cadence software compares P-FF's performance in CMOS 45nm and 90nm technology.