A Novel Approach to Design and Verification of a Pipelined Microprocessor with Hazard Detection and Stall Insertion

Since their conception in the early 1970s, microprocessors have been put to a multitude of uses through various different designs. While there are many academic papers on the implementation of a microprocessor, only a few are devoted to verification. Design and verification go hand in hand with every stage of a digital circuit implementation. In this paper, we propose a RISC pipelined processor with hazard detection, automatic hazard resolution, and automatic stall insertion. We incorporate a modular approach to design. We proposed a constrained random verification environment to fully verify the design with coverage based verification. Finally, this study implements the processor in real hardware to demonstrate operational ability. The proposed approach could easily be scaled up to design, verification and implementation of a large scale system on chip manufacturing.