Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars

This article presents a chopperless ripple-free low-noise bandgap reference (BGR) circuit in a traditional CMOS process that uses only p-n-p bipolars. Almost all chopperless bandgap structures require the use of n-p-n bipolars in special twin well processes, and they are prone to substrate and power supply noise. This work has targeted the “chopperless” scenario in p-n-p bipolar-based bandgap architecture by presenting a low offset temperature coefficient (TC) preamplifier design in the error amplifier. Notably, the design’s worst case power supply rejection (PSR) was “derived, simulated, and experimentally measured” to be −35 dB at 7.5 MHz, which is above par with any previously designed circuits. Furthermore, for the first time, an extensive mathematical analysis is provided for the self-bias loop, which is traditionally used to suppress the systematic offset. The prototype implemented in the TSMC 65-nm low-power (LP) process is untrimmed and occupies an active area of 0.0226 mm2 while drawing a current of $48.36~\mu $ A from 0.9-V supply. Measurement results of 28 chips and 10 chips in two different wafers show that the achieved nominal reference voltage of 500 mV has an average accuracy of 27 ppm/°C, similar to the curvature uncompensated BGR that uses chopping. Furthermore, the measured noise spectral density at 1-Hz offset is $10~\mu $ V/ $\sqrt {(}\text {Hz})$ , which is the state of the art among chopperless bandgap structures.