Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell Design

Nowadays, minimizing static power dissipation is a critical challenge in electronic systems as technology is moving into the nanoscale regime. Semiconductor devices are greatly affected by the short-channel effects and other process and parametric variations. A novel and comprehensive circuit-level technique is needed to maintain a sufficient manufacturing yield while balancing area, robustness, and power. A substitute for bulk devices in static random-access memory (SRAM) design is the FinFET (fin-field effect transistor) device-based design. Based on the literature, multiple techniques have been explored in previous years to reduce static power dissipation. Still, they have only successfully reduced a small percentage of static power. In this work, we developed a hybrid approach for designing six transistors (6T)-based SRAM cell using FinFET technology. The projected approach significantly reduces the amount of leakage current and leakage power in standby mode without any additional area cost. We achieved reductions of 26% and 32% approx., respectively, in the analysis of leakage current and static power dissipation as compared to the ordinary 6T SRAM design based on the FinFET technology. The simulation is performed in the cadence virtuoso environment at a 45 nm technology node. Since the FinFET device lowers static power dissipation by minimizing short-channel effects, it is a desirable semiconductor technology for designing nanoscale memory circuits in the future.