Design and Implementation of 5-Stage Pipelined RISC-V Processor on FPGA

This paper presents the design and implementation of a 32-bit, in-order, 5-stage pipelined RISC-V processor, executed on the Basys 3 Artix-7 FPGA. RISC-V, an open-source Instruction Set Architecture (ISA), has gained significant attention due to its simplicity, scalability, and modularity. Our focus is on implementing a processor core adhering to the RV32IM ISA, which incorporates static branch prediction and a hybrid encoding approach using both one-hot and binary encoding schemes. The primary motivation is to develop a RISC-V processor that is not only accessible for beginners but also sufficiently lightweight for deployment on modest FPGA platforms. The processor integrates a Universal Asynchronous Receiver Transmitter (UART) peripheral, designed using a finite state machine (FSM), transforming it into a basic System-on-Chip (SoC). The design and implementation were carried out using SystemVerilog within the Vivado Design Suite 2023.2. Functional verification was conducted through simulation using the Vivado Simulator, and further validation was achieved by monitoring output data on a serial terminal post-FPGA implementation. The processor achieved a maximum operating frequency of 65 MHz and consumed a total chip power of 119 mW. This paper provides a comprehensive overview of the literature, details the design methodology, describes the experimental setup, and offers a comparative evaluation with similar processors.