A 2 A Dual Loop LDO With Dynamic Negative Feedback Loop and Gm Boosting Error Amplifier for Off-Chip and Cap-Less Applications

This paper proposes a dual loop low-dropout regulator (LDO) for heavy load current (I $_{\mathbf {L}}$ ). The proposed LDO features a fast load transient response and wide output capacitor (C $_{\mathbf {O}}$ ) range. The proposed dynamic negative feedback loop (DNFL) enhances the transient response by reducing the undershoot and widening the bandwidth. The transient response is improved further by the proposed dynamic G $_{\mathbf {m}}$ boosting error amplifier. The C $_{\mathbf {O}}$ range gets wider thanks to the proposed DNFL, which introduces an additional zero in the feedback loop. The zero secures stability in a wide C $_{\mathbf {O}}$ range. The prototype of the proposed LDO is fabricated in a 0.5- $\mu $ m CMOS process. The input voltage (V $_{\mathbf {IN}}$ ) ranges from 2.7 to 4.2 V, while the output voltage (V $_{\mathbf {O}}$ ) ranges from 2.4 to 4.0 V. The maximum I $_{\mathbf {L}}$ is 2 A. The prototype provides enough phase margin across a C $_{\mathbf {O}}$ range from 0 to $1~\mu $ F. The measured results show a 68-mV undershoot with a load current of 2.5 A/ $1~\mu $ s on a 0- $\mu $ F C $_{\mathbf {O}}$ capacitor. When the C $_{\mathbf {O}}$ is $1~\mu $ F under the same conditions, the proposed LDO features an undershoot of 13 mV. The proposed LDO achieves the best FoM among the state-of-the-art LDOs without and with the off-chip C $_{\mathbf {O}}$ . In cases where the off-chip C $_{\mathbf {O}}$ is not employed, the achieved FoM is 5.228 ps $\cdot V/\mu $ m2. When using the off-chip C $_{\mathbf {O}}$ , the FoM is 0.624 ps/ $\mu $ m2.