Design and Implementation of a Winograd-Based Convolutional Neural Network Accelerator

Aiming at the problem that convolutional neural networks need to consume a large number of computational units and have a high computational complexity in embedded systems, this paper proposes a Dedicated Hardware Accelerator for VGG16-XDSC network based on Winograd algorithm. VGG16-XDSC is a lightweight network that consists of Depthwise Convolution and Shared Kernel sliding on channel Convolution, which is able to reduce the computational complexity and model size of the network while maintaining high accuracy. In order to further improve the computational efficiency of VGG16-XDSC, a series of accelerated optimization methods are proposed on the hardware side, including the shared computation engine of 1D Winograd and 2D Winograd, the merging processing unit of input transformations and the corresponding elemental multiplication, and avoiding the repetitive row transformation operations through row transformation optimization, utilizing the principle of 1D convolution kernel decomposition and the operations such as the 16-bit moving point quantization which further improves the computational efficiency of the network. The experimental results show that in the synergistic acceleration through algorithms and hardware architecture, the VGG16-XDSC gas pedal based on the Ultra96 V2 FPGA development board achieves 30.1 FPS with only 268 DSPs, and the energy efficiency reaches 13.44 GOPS/W, which accelerates the VGG16 more than ordinary Hardware accelerators.