Design and Analysis of 16-bit Modified Vedic Multiplier

In digital signal processing, the fast and highperforming Vedic multiplier (VM) is employed. Sixteen sutras, or formulas, form the foundation of Vedic multiplication. The multiplication of two numbers in this work is done using the Urdhva Tiryagbhyam (UT) sutra. This paper presents a modified Vedic multiplier (VM) which provides high computational speed, low power consumption, and minimal space requirements as an extra bonus. The Xilinx 14.7 software tool is used to design a 16-bit modified Vedic multiplier. The results are compared with VMs based on Carry-Save Adders (CSA) in terms of power usage, area, and delay. These parameters’ comparison shows that the updated multiplier offers significant improvements.