FPGA-based Digital Twins to Evaluate Test Coverage of Behavioral Failure Modes

Generally, there is no way to know whether tests - performed on automatic test equipment (ATE), by built-in test (BIT) or by other means detect all failures. To evaluate test coverage, one would need to encounter a particular failure to be sure that the test indeed detects it. A Digital Twin (DT), which mimics product behavior is typically created in parallel with product development. It can provide a simulation and emulation of both good and faulty versions of the unit under test (UUT), or the physical twin (PT). At the early-design stage Failure Mode and Effects Analysis (FMEA) should also be available for failure modes affecting product behavior. Behavioral failure modes, unlike structural failure modes, are independent of implementation details and tests can be evaluated (to be Valid) even before detailed design is undertaken. A test that cannot detect a behavioral failure mode is ineffective (Invalid) and will require a change in either the test or in the product, something which we need to know for products being designed or already fielded. When no Valid test is possible, the failure mode is untestable and only a design change can cure that. It is best, if we know early in the design stage, before expensive redesign becomes necessary. We propose a DT that uses a Field Programmable Gate Array (FPGA). An FPGA allows the execution of more critical real-time operations than a software-based DT could. Additionally, the reconfigurability of an FPGA allows us to “inject errors” by replacing the FPGA configured for a “Good” UUT with a configuration that contains a particular “failure mode” variant. Since the number of behavioral failure modes is relatively small, it is not difficult or time-consuming to create “Faulty” FPGA DT models to emulate each single occurrence of failure modes. The FPGA variant we propose is the System on Programmable Chip (SoPC), in which the programmable logic (PL) area can be partially configured. Since the SoPC contains a processor that manages the configuration of PL partitions, an almost unlimited number of failure mode configurations can be retrieved from an external storage medium. This will allow us to extend this concept to structural models and failure modes, which would likely involve thousands of “Faulty” DTs. The paper will also investigate how a list of failure modes entered into the DT can readily (if not automatically) create the variant faulty UUT model for each failure mode.