Performance Optimization in 3D Flash Memory Cell Stack via Process Variable Engineering

While three-dimensional (3D) semiconductor devices have been extensively studied to overcome the intrinsic physical limits imposed by the continuous scaling down, the impacts of various process variables have not been sufficiently investigated. In this work, the impact of various process variables on the structure and electrical characteristics of a vertically stacked 3D flash memory cell stack is thoroughly investigated. Based on the fabricated devices and TCAD simulations, comprehensive analyses are performed on various characteristics, including cell current, gate controllability, inter-floor cell interference and variation, voltage drop issue, bottom cell failure issue, and cell density. We provide optimization guidelines with trade-offs to enhance device performance.