An $8\times 1$ GS/s Time-Interleaved ADC Model and Background Calibration for Mismatch

This article presents a TIADC model based on Verilog-AMS with the sub-ADC adopting pipeline ADC. The TIADC has 8 channels with a single-channel sampling rate of 1GS/s and a total sampling rate of 8GS/s with 12-bit resolution. It also completed the calibration of the offset mismatch, gain mismatch and timing skew. The paper uses iterative averaging algorithm for offset and gain calibration. With 2us calibration SNDR and SFDR can be improved by more than 20dB.