A Wide-Range Delay Lock Loops for Pipelined ADCs

Traditional clock units, predicated on inverter delay lines, are constrained and often inadequate for the demands of high-precision analog-to-digital converters (ADCs). This paper introduces a novel wide-range, low-power Delay-Locked Loop (DLL) tailored for pipelined ADCs, designed using a 152 nm CMOS process. The proposed DLL features a dual-path delay unit that modulates the output signal's delay time through the dynamic control of a charging and discharging mechanism. This innovation significantly expands the operational frequency range of the delay line and ensures precise control over the delay period. Simulation results indicate that the DLL operates efficiently within a broad spectrum of 170 MHz to 630 MHz under a 1.8V supply voltage. Notably, with an input reference clock signal at 500 MHz, the DLL achieves an impressive peak-to-peak jitter of 1.16 ps and a low power consumption of 1.54 mW. This advanced DLL is capable of generating the requisite five-phase clock for pipelined ADCs, adeptly fulfilling their stringent operational requirements.