A Compensation Principle for the Temperature Sensitivity of in-Memory Computing Arrays

With the development of technologies such as image processing and speech recognition, in-memory computing chips are being designed and developed for use in terminals or wearable devices, which pose a challenge for their stability under extreme temperatures. In addition, many in-memory computing circuits are implemented analogically and are more sensitive to temperature changes than digital circuits. In this paper, we proposed a temperature compensation circuit based on the principle of temperature sensitivity coefficient cancellation for in-memory computing arrays. We applied the Iris dataset to the proposed schematic circuit to implement the classification function. The maximum total relative error is less than 0.15% in the temperature range of −40°C to 85°C, which is lower by 22 times than before compensation. The error rate of the Iris classification decreases by more than 24.9% at temperatures below 0°C or above 50°C.