Design and Implementation of AHB to APB Bridge and AHB to UART Communication for SoC Integration

The AHB is a vital component in the AMBA family, deSigned to prioritize high performance, reduced power consumption, and efficient data transfer. Its main purpose is to facilitate communication between various system components. The APB is used to connect peripheral devices with lower data demands, employing a simple, non-pipelined protocol for data exchange between a master unit and multiple peripherals via a shared bus. This project focuses on implementing an RTL design of an AHB to APB bridge comprises of AHB slave interface, state machine and APB interface, including simulation of read and write operations. Furthermore, it also proposes integration of UART with the AHB interface by the FIFO buffer. This AHB to APB bridge enhances the functionality of System on Chip (SoC) configurations, especially those involving multiple masters and slaves, by effectively managing data transfers. Xilinx Vivado is utilized as the verification environment for this project, with Verilog as the chosen Hardware Description Language (HDL).