Implementation of IC Segregation and Testing Using FPGA

This paper presents the development of an Integrated circuit (IC) segregation and testing system that combines mechanical models, FPGA (Field programmable gate arrays)-based image processing for segregation, and reconfigurable input/output configurations, oscillator circuit, DUT (Device under test) unit for testing. The system aims to automate the process of IC segregation, improving efficiency and accuracy. Key components of the system include orientation rectification, conveyer belt sequencing, IC identification through image capture, Sobel edge detection for text extraction, and IC classification based on testing requirements. The system is controlled by an Altera DEI FPGA board, interfacing with various peripherals and components to perform comprehensive IC testing and segregation.