ESD and Latch-Up Design Verification Challenges in Packaged Parts and Modules

ESD and latch-up stress testing to meet industry standards is performed on packaged parts and modules. However, ESD and latch-up design verification has been historically done on die / silicon database. In case of inadequate protection, ESD and latch-up damage occurs on silicon. However, package and module configurations play a significant role. Packages and modules based on the same silicon die can have very different ESD and latch-up protection levels. In this paper we review package and module properties impacting ESD and latch-up protection. These properties include package and module size, capacitance, package wire connectivity and inductance. We discuss ESD and latch-up EDA challenges in packaged parts and modules. We propose a new verification flow to access ESD and latch-up on package and module levels as well as outline the implementation steps.