Impact Analysis of Negative Gate Voltage on SiCMOS Reliability Under OFF-State Avalanche Stress

This paper fully researches and analyzes the effect of negative OFF-state gate-source bias voltage (VGS, off) on the device degradation under OFF-state avalanche stress. It is found that the degradation associated with negative VGS,off is much greater than that of 0V VGS,off and negative bias temperature instability (NBTI). While the shift in threshold voltage (VT) and on-resistance (Ron) are relatively small, and the biggest change is reverse leakage current (IDss) corresponds to the generation of interface state. This phenomenon is analyzed in conjunction with Technology Computer Aided Design (TCAD) analysis, which demonstrate that under the avalanche stress condition, the electric field at the bottom of the gate oxide attains substantial magnitudes. Moreover, the introduction of negative VGS,off significantly amplifies the electric field in this region, which has a significant impact on the long-term reliability of the device.