High-Speed Triple Operand Adder for Graphic Processing and Cryptography

Consumer Electronics industry has triggered a notable surge in the need for high-performance products, and huge operands with low-power adders. Many operands require a lot of energy when using standard fast adder designs like parallel prefix adders. Hybrid designs offer a viable solution to the problem of striking a balance between power consumption and latency in large operand addition. The least significant carriers in large parallel-prefix adders are generated significantly faster than the most significant ones; this insight is capitalized upon in this work hybrid adder architecture for enormous operands. Due to the lack of significant impact on overall performance, this work does not to include fast ideas relating to this issue when applying carries to the final computing of the least-significant bits. Thus, without sacrificing speed, this method minimizes the size of the summing blocks at the least important locations. In order to further minimize latency, the suggested adder's carrier network generates and distributes the complement of the carries. Comparing this proposed adder to the most advanced adders for big operands, VLSI (Very Large Scale Integration) implementation findings utilizing 45-nm-TSMC technology show that it offers a reduced area-delay product and consumes less energy.