Design of 4-Bit Synchronous Counter Using TSPC-SVL T Flip-Flop for Power Reduction

The primary objectives of low-power VLSI circuits are to enhance system performance by decreasing power consumption, optimizing chip sizes, and extending battery life. Scaling designs, like counters, can adjust system parameters based on previous states, enabling tracking of time and frequency. However, power consumption, particularly in standby mode dissipation, remains a key challenge for scaling circuits. The clock signal in a counter consumes one-third of its power. In this study, the number of switching actions is limited to reduce power usage. By lowering the flip-flop's power consumption, the counter's power consumption was further decreased. This could be achieved by combining SVL (Self-Controllable Voltage Level) with TSPC (True Single Phase Clock), and 6 transistor XOR gate. This 4-bit counter was designed with 45nm technology and Compared to the existing design, the new one consumes 27% less energy.