Design and Optimization of Universal Shift Registers Using Novel Reversible Logic Gates

Reversible logic is gaining increasing significance in diverse research areas, including quantum computing, nanotechnology, and optical computing. The exploration of reversible gates has emerged as a cutting-edge research area, driving a wave of innovative developments aimed at maximizing resource efficiency. Adders are essential in multipliers, especially in digital signal processing (DSP) applications. Reversible logic gates represent a major breakthrough in digital circuit design due to their ability to perform operations without loss. In this research work, demonstrated reversible Master-Slave D-flipflop (RDFF) and a 4×l Multiplexer (RMUX), we were able to effectively implement the design of a universal shift register. A number of essential metrics, including as garbage outputs (GO) and quantum cost (QC), provide proof that our suggested design is successful. We have achieved a decreased power consumption, a minimal quantum cost, and a reduced number of reversible logic gates and garbage outputs, all of which contribute to the accomplishment of our design. Validation and simulation of the reversible 4-bit universal shift register circuits (4-bit RUSR) were carried out in Xilinx Vivado 2022.2 software.