Enhancing Lightweight Embedded Systems with Network-on-Chip Based Memory Organization Unit

In the realm of integrated circuits (ICs), efficient memory management is pivotal for enabling high-performance computing in modern applications. With the rise of lightweight processors and the Internet-of-Things (IoT) era, there is an increasing demand for multiprocessing capabilities in ultra-low-power (ULP) embedded devices. To improve the performance of the ULP devices we propose an architecture in which an memory organization unit (MOU). MOU is introduced where network-on-chip (NoC) can provide the advantage of introducing it in existing ULP devices. Segmented paging approach is used in designing MOU architecture to provide advantage in memory utilization and fragmentation. The simulated result of the current research shows implementation of segmented paging which are varied by different valid bits for each segment when accessed by processor.