Efficient Data Comparison through Multiplexer Logic for Low Power and Low Area

A Multiplexer logic is a novel and low-power, effective method for creating a data comparator. As the core processing component of the data comparator, the suggested approach uses a borrow equation utilizing multiplexers setup inside of a complete subtractor. To increase this model’s usefulness and cross-platform adaptability, it was developed in Verilog for simulation using the Cadence tools. The successful reduction in transistor count, accomplished by incorporating a revised borrow equation using multiplexers in the complete subtractor design, directly contributed to decreased power consumption. Moreover, an analysis conducted spanning all technologies showed significant drops in physical space and power consumption with the progression from 180 nm to 90 nm and then to 45 nm technologies. These observations demonstrate considerable possibility for power and space efficiency gains in real-world applications of image processing.