IP Security in Structured ASIC: Challenges and Prospects

With the globalization of hardware man-ufacturing and the growing demand for electronics, companies now heavily rely on offshore facilities for most of the design and manufacturing processes, in-cluding emerging technologies like Structured ASICs (Application Specific Integrated Circuits). This trend has prompted hardware designers to consider adopting a zero-trust model, acknowledging the possibility of malicious access to sensitive information at any stage of the design flow. Existing security solutions do not address these vulnerabilities for structured ASIC and are only designed to protect against limited attack surfaces. In this paper, we analyze the IP security issues in structured ASIC and discuss solutions to address them. We point to a layered approach for IP protection, where the unused resources in configurable logic blocks are utilized to minimize overhead costs.