PACE: MLP-Based Fast and Accurate Per-Cycle Chip Power Modelling

Designing power-efficient chips is increasingly im-portant with the end of Dennard scaling and the growing demand for improved chip processing performance. Chip design and assessing its power closure are lengthy processes requiring mul-tiple turnarounds. The gate-level power estimation, the adopted industrial approach, is too slow and impractical for large-scale designs and long workloads. Alternatively, one can model power at higher abstraction levels to accelerate the power estimation flow. PACE is proposed as a fast and accurate register transfer level (RTL) power estimation model for CPU designs. Our machine learning based approach depends on switching activities of register bits sourced from RTL simulation and offers cycle-accurate power prediction. It employs LASSO for identifying the most critical register bits for power estimation and utilizes sparse Multilayer Perceptron (sMLP) on the selected register bits. PACE surpasses LASSO and APOLLO in accuracy and outperforms PRIMAL in inference speed and scalability among RTL power models. This combination of higher accuracy, faster speed, and improved scalability elevates PACE as the preferred option for power prediction.