RFET-Based Dynamic Differential Logic Cells Against Power Side-Channel Attacks

Power Side-Channel Attacks are effective attacks that utilize the dependency between data and power consumption of the circuit to extract its secret information, like the encryption key of cryptographic circuits. Several circuit-level power equalization methods, such as Dynamic Differential Logic (DDL), have been proposed to provide almost data-independent power consumption. However, the high energy and area overheads of these countermeasures hinder their deployment in resource-constrained systems, and sometimes, they cannot completely resolve the intrinsic vulnerabilities of CMOS-based circuits. In recent years, Reconfigurable Field-Effect Transistor (RFET), an emerging transistor with runtime reconfigurability between P- and N-type and multiple independent gate support, has shown great potential in providing low overhead hardware security solutions for IP protection and SCA-resiliency. This paper proposes RFET-based power-balanced cell designs for two DDL families, Wave Dynamic Differential Logic (WDDL) and Dynamic Differential Cascode Voltage Switch Logic (DyDCVSL). To evaluate our designs, we implemented the Piccolo S-box and analyzed it using widely used power variation metrics. We also performed a CPA attack on this circuit to assess the security of our design under an actual attack. The results show that our design delivers a higher power SCA resiliency with lower energy and area overheads comparing its CMOS-based counterpart.