Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC

Thermal challenges in 3D-IC arise from the high thermal resistance of the 3D interface layer and Back-End-Of-Line (BEOL), leading to poor heat dissipation & increased peak junction temperature. In this study we analyze the impact of technology and material parameters of Embedded micro-Bumps $(\mathbf{E}-\mu \mathbf{Bumps})$ and Wafer-to- Wafer (W2W)-Hybrid Bonding (HB) on thermal behaviour of the package stack. Thermal analysis is conducted on a 64-core SoC with power density of $140\ \mathrm{W}/\text{cm}^{2}$ using advanced A14 nanosheet CMOS technology. Simulation outcomes demonstrate that as the amount of metal in the 3D interface increases (relative to dielectric) from 0% to 20%, the peak temperature $T_{max}$ of $\mathbf{E}-\mu \mathbf{Bumps}$ decreases by 20%, beyond which $T_{max}$ is limited by the BEOL thermal resistance. The study demonstrates that at 20% metal density, the thermal impact of stand-off height is negligible, regardless of 3D interface technology. Among 2-die stacks, Memory-on-Logic (MoL) configuration exhibits the highest $T_{max}, 5{}^{\circ}\mathbf{C}$ above the 2D baseline, while 3-tier stack increase $T_{max}$ by $12{}^{\circ}\mathbf{C}$, necessitating an extra 33% heat transfer efficiency to reduce $T_{max}$. Additionally, for BEOL analysis, introducing backside PDN, results in $2{}^{\circ}\mathbf{C}$ increase for 2D and $2{}^{\circ}\mathrm{C}$ reduction for 3D (MoL) configurations.