CoNfasTT: A Configurable, Scalable, and Fast Dual Mode Logic-Based NTT Design

This paper presents a scalable, fully-unrolled Number Theory Transform (NTT) architecture that eliminates memory registers. This architecture leverages Dual-Mode Logic (DML) technology to achieve configurability for various input sizes $(N)$ and bit-widths $(K)$ . The design targets hardware acceleration, aiming to deliver NTT functionality at the speed of signal propagation without relying on registers or incurring pipeline-related trade-offs. Our implementation offers several potential optimizations, including a unique, fully-combinational, and low-cost modular reduction technique within the K-RED algorithm. Furthermore, it eliminates memory access penalties and control overhead. The widespread adoption of NTT and similar repeated structures across various fields underscores the broad applicability of our findings. Similar to large-scale DML-based architectures (e.g., MAC multipliers), our DML-NTT design can optimize both performance and energy consumption compared to standard CMOS implementations. Evaluation against its CMOS counterpart and a diverse set of existing hardware NTT implementations demonstrates high efficiency. For instance, an NTT with $N = 2^{10}$ and $K = 2^{5}$ bits achieves either high energy efficiency ( $0.227~\mu $ J in static mode) or superior performance ( $0.018~\mu $ s in dynamic mode). These results surpass all known synchronous/iterative (rolled) or memory-based designs to date. Compared to an unrolled CMOS implementation, our design offers a 2x performance improvement in dynamic mode, albeit at a 5x energy cost. Additionally, the design incorporates a static mode that exhibits performance nearly identical to the unrolled CMOS architecture, providing flexibility for design considerations.