Metal Fill-Induced Timing Effects: Unraveling Parasitics in Network on Chips

In semiconductor design, challenges posed by the chemical-mechanical polishing (CMP) process are accentuated by the unintended timing degradation from conventional metal fill, due to its capacitive and resistive attributes. To counteract these effects, this paper presents the Emulated Metal Fill technique, designed for early estimation of metal fill-induced timing ramifications. When applied to various Network on Chips, this method notably optimized congestion and routing DRCs, curtailed power consumption by 8.95%, safeguarded 60% of ECO cycles, and impressively achieved a 99% timing accuracy rate. These outcomes underscore the technique’s promise as a robust alternative in semiconductor design.