A Comparative Study of CMOS and Finfet Sram Cells: Leakage Minimization and Energy Optimization

This work presents a comparative analysis of the performance characteristics exhibited by two established SRAM cell topologies, namely the conventional 6 and the 7 transistor designs, with as well without using the KLECTOR Technique in 180nm, 90nm, 45nm Technology. Specifically, each SRAM cell's power usage and leakage currents are compared and analyzed between CMOS and FinFET. Using KLECTOR Technique reductions can be seen in power Consumption (which are 30–45 percent in 6T and 30–52 percent in 7T) and Leakage Current (which are 20–30 percent in 6T and 18–30 percent in 7T). Also, the design of 6 as well 7 transistor FinFET static RAM cell with and without using the KLECTOR Technique is implemented at 18nm technology. According to the simulation results, designing SRAM cells using FinFET may be much more efficient than designing CMOS SRAM cells, as demonstrated by the significant reductions in power consumption (which are 53 percent in 6T and 74 percent in 7T) and leakage currents (which are 80 percent in 6T and 66 percent in 7T). Additionally, the Read and Write Delay of FinFET and CMOS transistors is analyzed and compared. This work aims to lower power consumption and leakage current by utilizing the Cadence tool and a 0.8V supply voltage.