Implementation and Evaluation of Approximate Multiplier for Improved Efficiency

Multipliers stand as essential components that play a pivotal role in computational tasks. Their importance is found not just in achieving accurate and high-speed calculations but also in optimizing power efficiency. Approximate multipliers are useful in applications where a modest level of imprecision is tolerated but does not affect the overall outcome. In this paper, two approximate 4:2 compressors are proposed and utilized in an 8 × 8 Dadda multiplier. By strategically introducing controlled approximations, by sacrificing precision, multipliers with proposed approximate compressors offer reduction in power consumption, area utilization, and delay, by compromising on accuracy. The error analysis is further verified on the scales of Error Rate (ER), Error distance (ED) and multiple other metrics. Xilinx Vivado software is used to simulate and synthesize the proposed designs.