Genetic Algorithm Based Method for Escaping Routing Congestion in VLSI Circuits

In recent years, the functionalities within Very Large-Scale Integration (VLSI) circuits have steadily increased. This makes maintaining performance while keeping the physical size consistent quite challenging. As a result, manual routing is no longer cost-effective. Hence, Automatic Routing[4] has become the preferred method for modern VLSI layout design. This paper proposes an Automatic Routing method using a Genetic Algorithm (GA), a Metaheuristic Algorithm. This method enables automated routing to the boundaries. The Genetic Algorithm aims to minimize routing pathways, focusing on achieving the shortest routes while adhering to predefined constraints. This algorithm is smoothly integrated into the circuit model. By using the Genetic Algorithm in this way, we aim to enhance the efficiency of VLSI routing, addressing the challenges brought on by the increased complexity of integrated functions within VLSI circuits.