A 10-bit 300MS/s Time-Interleaved Successive-Approximation Register Analog-to-Digital Converter with a Binary-Scaled Recombination Weighting Capacitor Array and fault-tolerant

An asynchronous Successive-Approximation Register (SAR) Analog-to-Digital Converter (ADC) with redundant ability is designed to achieve high speed and high resolution. The binary recombination weighting algorithm is utilized to reduce the conversion error. Then, the time-interleaved parallel technology is adopted with two sub-channel ADCs operating to increase the maximum sampling rate. A double-ended input method is implemented to reduce the common mode noise effectively. The simulated static performance DNL is 0.498/-0.512 LSB, and the INL is 0.513/-0.515 LSB. Under the sampling frequency Fs of 300MHz with Fin of 60MHz, the dynamic performances of SNDR and SFDR are 55.08dB and 66.915dB, respectively. The ENOB is 8.857 bits, and the FoM is 32.6 (fJ/conv.-step).