An Enhanced Power-Delay and Area Efficient Dual Output Subthreshold Level Shifter

This paper presents an enhanced power-delay and area efficient subthreshold level shifter (LS) with dual outputs. By inserting current limiters into pull-up network, the proposed LS can operate in subthreshold voltage domain. Combined extra voltage stress limiters with multiple voltage CMOS technique, the dual output can be achieved with area efficient consumption. Post-layout simulation results in a 40 nm CMOS technology illustrate that the proposed LS can step up voltage as low as 130 mV at 200 KHz. With an area of $51.6 \mu \mathrm{m} 2$, the power dissipation and delay of proposed LS are 77.62 nW and 2.75 ns when transforming a 0.4 V signal to 1.0 and 1.8 V at 1 MHz.