Ultra-low Loss Current Enhancement SiC Planar Gate IGBT with Composite Barrier Structure

A novel current enhancement silicon carbide (SiC) planar gate insulated gate bipolar transistor (IGBT) with composite barrier (CB) structure (CBCE-IGBT) is proposed and analyzed in this paper. Combined with the P-shield layer in the junction field effect transistor (JFET) region, dual hole barrier provided by the featured CB structure not only reduces the electric field in the gate oxide layer in the blocking state but also enhances the conductivity modulation and then optimizes the carrier distributions in the $\mathbf{N}$-drift region in the conduction state. Consequently, an ultra-low loss SiC IGBT is obtained with improved reliability. Simulation results show that the on-state voltage drop ($V_{\text {ceon }}$) of the proposed CBCE-IGBT is only 4.5 V at the collector current density $\left(J_{C}\right)$ of $100 \mathrm{~A} / \mathrm{cm}^{2}$, which is 0.47 V and 2.11V lower than that of the SiC IGBT with current enhancement layer (CEL-IGBT) and conventional SiC IGBT (Con-IGBT), respectively. At the same Vceon of 6.4 V, the turn-off loss ($E_{\text {off }}$) of the proposed CBCE-IGBT is $16.5 \%$ and $71.7 \%$ lower than that of the CEL-IGBT and Con-IGBT, respectively. It realizes a superior $E_{\text {off }}-V_{\text {ceon }}$ trade-off relationship. The heat generated and temperature raised for the proposed CBCE-IGBT during turn-off period are significantly reduced due to its lower $E_{\text {off }}$, which exhibits enhanced turn-off ability under large current and high temperature. The proposed CBCE-IGBT can be turned off effectively at the temperature of 450 K and 4 times of nominal working current without experiencing any deterioration. In addition, the fabrication of the proposed CBCE-IGBT is compatible with the Con-IGBT and CEL-IGBT.