A 1.55-to-5.25 GHz Ring Oscillator PLL with Supply Insensitive Current Clamp Loop Technology

A ring oscillator (RO) phase-locked loop (PLL), featuring supply-insensitive current clamp loop (SICCL) technology, is proposed for clock synthesis in system-on-chip (SoC) applications. SICCL technology aims to deliver a consistent current to the RO across a broad range of power supply variations. Implemented in a 65-nm CMOS process and operating within the frequency range of 1.55 to 5.25 GHz, the proposed RO PLL with SICCL technology exhibits a power consumption of 6.6mW under a 1 V supply voltage. Simulation results showcase its performance, achieving static and dynamic supply noise immunity of 0.003%-fout/1%-VDD and 2.6%-fout/1%-VDD, respectively, at 3.9 GHz. Notably, it demonstrates an 824 fs rms jitter with a Figure of Merit (FOMj) of -233.5 dB.